It is known that memory devices, such as non-volatile memory devices like EEPROMs and Flash EEPROMs, comprise a memory cell array arranged in rows (word lines) and columns (bit lines). Each memory cell is substantially formed by a MOS transistor comprising an electrically insulated gate electrode, a control gate electrode, a drain electrode and a source electrode.
The control gate electrode of each cell is connected to a respective row of the array, and similarly the drain electrode is connected to a respective column; the source electrodes of the cells are all connected to each other.
The memory cell array can be formed directly in the substrate common to the entire semiconductor chip wherein the control circuitry is also integrated. In this case, a bulk electrode of the memory cells is biased as a substrate potential, generally a reference potential.
Non-volatile EEPROM and Flash EEPROM memory devices are known wherein the memory cells are fabricated inside a first semiconductor material well with a dopant of a first type (e.g., P-type), said first semiconductor material well being in turn contained within a second semiconductor material well with a dopant of a second type (e.g., N-type) that isolates the first semiconductor material well containing the memory array from the substrate. Devices manufactured of this kind are generally called "triple well devices".
In this way, i.e., the triple well configuration, it is possible to bias the bulk electrode of the memory cells at a potential different from that of the substrate. This is particularly advantageous for Non-volatile EEPROM and Flash EEPROM memories because it allows different methods for performing reading, programming and erasing operations, particularly in view of a possible reduction in the current consumption during said operations and/or of the use of lower supply voltages for the memory device.
A drawback of the use of a triple well device is given by the fact that the first semiconductor material well with dopant of the first type containing the memory cells, due to its limited depth, has a higher resistivity than the substrate does. This can cause undesired electric potential differences between different zones of the memory array during the operations involving significant bulk currents (such as, for example, programming and erasing operations). In a conventional memory array wherein the memory cells are formed directly within the substrate, it is sufficient to contact the substrate along the periphery of the array to guarantee that the bulk electrode potential of the memory cells is substantially constant within the array. This is however not sufficient for a memory array formed inside a triple well device.